1. Field of the Invention
The present invention relates to a data processor which performs pipeline processing in response to an instruction stored in the memory.
2. Related Art
Due to the recent developments in the field of electronics, information processing devices, such as microcomputers, have been widely used in various areas.
Conventional information processing devices can be classified roughly into two types: Complex Instruction Set Computers (CISC) which can execute a large number of instructions of various types, and Reduced Instruction Set Computers (RISC) which limit instructions to certain types, but increase the speed at which the computers executes the instructions. The former includes a TRON specification chip and Motorola's MC68040, while the latter includes Sun Microsystems' SPARC and MIPS Technologies, Inc.'s MIPS. These processors have a pipeline structure to reduce the apparent instruction execution time. With such pipeline structure, the instruction processing is divided into at least three stages: instruction fetching, decoding, and execution. These stages can be performed in parallel.
FIG. 1 is a block diagram of a data processor of a conventional information processing apparatus.
In this figure, a data processor 7 comprises: an instruction fetch circuit 71 for fetching an instruction from a memory (not shown) in an instruction fetch stage (hereinafter referred to as IF stage); an instruction decoding circuit 72 for decoding the instruction fetched by the instruction fetch circuit 71 in an instruction decoding stage (hereinafter referred to as DEC stage); and an instruction execution circuit 73 controlled by the instruction decoding circuit 72 in an instruction execution stage (hereinafter referred to as EX stage). This data processor 7 has a pipeline structure consisting of the above three stages. The instruction execution circuit 73 comprises: a register set 731 for storing the operand data of an operation; buses 732a to 732c for transferring the data read from or to be stored into the register set 731; and an operation unit 733 for executing an operation based on the data transferred by the buses 732a to 732c.
Referring to a timing chart shown in FIG. 2, the following explanation is for an operation in the case where the frequency of the operational clock is 50 MHz (megahertz), i.e., where the processing time of each stage is 20 nanoseconds, in the conventional data processor 7 having the structure described above.
An instruction fetched by the instruction fetch circuit 71 (IF stage: 8 nanoseconds) is decoded by the instruction decoding circuit 72 (DEC stage: 10 nanoseconds), and then executed by the instruction execution circuit 73 (EX stage: 19 nanoseconds). In EX stage, operand data designated by the instruction is read from the register set 731 (5 nanoseconds), inputted into the operation unit 733 via the buses 732a and 732b, calculated by the operation unit 733, and finally sent from the bus 732c to the register set 731 as an operation result (14 nanoseconds). The times shown above are the processing times required in the most time-consuming operations, such as an integer multiplication.
For an information processing apparatus having a pipeline structure, it is necessary to make each stage's processing time uniform and as short as possible. With the conventional information processing apparatus shown in FIG. 1, there is a variation in processing time. The processing time of EX stage is longer than any other processing time, and as a result, the upper limit of the operation clock frequency is low.
As described above, there is a problem in the conventional information processing apparatus in that the upper limit of the clock frequency is determined by the stage of the longest processing time, and such problem prevents an increase of the processing performance. There is another problem that, to make the processing time of EX stage substantially equal to other processing times, an extremely high-speed device and parallel processing are necessary, and as a result, the production cost and power consumption become larger.
The following is a detailed description of those problems with reference to an operation timing chart shown in FIG. 2. Since IF stage and DEC stage are completed in the first half of each machine cycle, these two stages can be performed at 100 MHz. However, the processing time of EX stage is 19 nanoseconds, much longer than either IF stage or DEC stage. As can be seen from the timing chart, the upper limit of the operation clock frequency depends on the processing time of EX stage, and the overall operation can be performed at 50 MHz nearly at the most.
In the case of a RISC-type processor, the processing times of IF stage and DEC stage can shortened by installing a high-speed instruction cache or by simplifying instructions, but at the same time, the processing time of EX stage is prolonged further due to the introduction of a highly functional operation unit. In the case of a CISC processor, DEC stage tends to be prolonged due to complicated variable-length instructions.
Particularly, as various types of data processing are performed by an extended processor so as to accommodate today's multimedia systems, the processing time of EX(E) stage is likely to be prolonged due to the introduction of a highly functional operation unit.